1. Field of the Invention
The novel invention relates to novel structures for Field Effect Transistors FETs, such as Heterojunction Insulated Gate FETs (HIGFETs) and Field Effect Infra-Red (FIRE) or FET IR detectors.
2. Description of Prior Art
HIGFET
The high mobility and large electron saturation velocities of compound semiconductors makes them attractive candidates for high speed and high frequency applications. In extremely small geometry devices the electrons are expected to experience collisionless ballistic transport through the active region of the device. This phenomenon is more easily observed in vertical heterojunction bipolar transistors (HBT) where the electrons enter the active region with considerable initial velocities. In HIGFETs, application of a suitable gate voltage lowers the semiconductor potential in the channel region under the gate region and causes electrons to be injected from the highly doped source into the channel. Transport occurs at the high mobility heterojunction interface and since the channel is completely undoped, scattering by ionized dopants is absent.
State-of-the-art Heterojunction FETs use a buried channel approach using epitaxial insulators, such as InAlAs or conventional dielectrics such as silicon nitride with a larger bandgap than the channel material, e.g. InGaAs. However, the forward gate-source breakdown voltage of epitaxially grown insulators is small, typically 1-1.25 volts, since the epitaxial insulators currently used have a much lower bandgap and resistivity compared to conventional dielectrics. Lattice matched or strained epitaxial growth of a high resistivity large bandgap material is a technological challenge and has not been adequately realized yet. There is also evidence that strain reduces the bandgap thereby further decreasing the confinement barrier. The lower barrier height will also limit the input gate voltage swing on enhancement type devices and restrict their high temperature operation. For these reasons, until a suitable high resistivity, large bandgap epitaxial insulator is developed there will also be interest in the use of conventional dielectrics for buried channel HIGFETs. Recently, Martin et al, reported a non-self-aligned buried channel HIGFET using SiO.sub.2 as the gate insulator in "Undoped InP/InGaAs heterostructure insulated gate FET's grown by OMVPE with PECVD deposited SiO.sub.2 as gate insulator", E. A. Martin, O. A. Aina, A. A. Iliadis, M. R. Mattingly and L. H. Stecker, IEEE Electron Device Lett. V9, pp. 500-503, 1988. These devices showed large transconductance due to carrier transport at the high mobility, buried heterojunction interface and a large allowable input voltage swing. However, a 20% drain current drive (DCD) over 10.sup.4 seconds at 300K and considerable hysterisis in the C-V characteristics indicate a significant amount of traps at the insulator/InP interface. Lowering the trap density at the top insulator/semiconductor interface will lower DCD and result in better modulation of the channel poteneial and increase the small signal response. In recent years interface passivation or interface control engineering is used to reduce the trap concentrations at the insulator/semiconductor interface. For example, Sulfur (S) passivation of the InP surface lowers the surface state density considerably by preventing the formation of Phosphorus (P) vacancies. This passivation process however is quite non-uniform and epitaxial passivation techniques can be used to improve uniformity.
In heterojunction FETs, numerical simulations indicate that the low electric field near the source region cause the electrons to enter the channel region with a low initial velocity and gradually accelerate towards the drain attaining the maximum drift velocity near the drain end of the channel. Device speed determined by the overall electron transit time of the channel region is therefore limited by the relatively slow electron drift velocity near the source region. This low field region limits performance in high frequency devices. Also, no effort has been made to date to improve the injection of carriers from the source region into the channel.
One of the objectives of the invention is to minimize these limitations by creating a built-in quasi field between the source and channel regions to speed up the electrons. An earlier approach to reduce transit time, uses a split gate to speed up the transistor (Ref: "Split gate field-effect transistor", M. Shur, Appl. Phys. Lett. V54, pp. 162-164, 1989). Here different voltages applied to two closely spaced gates changes the field distribution in the channel region. We present a new approach for a single gate FET, with a graded portion of the channel region near the source resulting in a large quasi-field near the source/channel junction. The field is used to launch the electrons at near saturation velocities into the channel region which would cause ballistic or quasi-ballistic transport depending on the device geometry. The field will also improve carrier injection from the source region.
Another objective of the invention is to use a thin epitaxial GaP passivation layer to reduce the interface state density in HIGFETs using conventional dielectrics and thereby increase the transconductance and frequency response of these devices.
FET Infra Red Detector
Conventional IR detectors use platinum silicide/p--Si Schottky barriers and narrow bandgap binary (e.g. InSb) or alloy semiconductors, (e.g. HgCdTe). Dark current is a reason for concern in both cases. The silicide/Si barrier height of 0.26 eV restricts the detector use to the 3-5 mm range while the breakdown field of narrow gap semiconductors is quite low. Materials technology and uniformity are rather difficult when narrow gap semiconductors are used. In addition these devices have to be cooled in order to minimize thermal excitation noise. The IR detector currently envisioned uses a large bandgap III-V semiconductor in contact with a smaller gap semiconductor. The latter layer has a larger electron affinity than the former and results in a conduction band discontinuity (.DELTA.E.sub.c) at the heterojunction interface and confined quantum states resulting in a two dimensional electron gas in the smaller gap material. Device operation is similar to the silicide Schottky device where the electron gas acts as the metal and .DELTA.E.sub.c represents the Schottky barrier. The photons interacts with the electron gas to produce hot electrons which are emitted across the .DELTA.E.sub.c barrier into the larger gap material. Carrier emission is aided by the presence of the field perpendicular to the surface. By choosing different materials or with different alloy compositions we can alter .DELTA.E.sub.c and thereby the operating wavelength. The device will be controlled by a gate electrode that depletes the active area between the samples minimizing thermal excitation noise. Consequently, the device is expected to be operated without cooling or at temperatures higher than conventional IR detectors. Moreover since large bandgap semiconductors are used, breakdown voltages are high.
The III-V compound semiconductor technology that is used to fabricate these devices is quite mature and the fabrication complexity is moderate. However, to fabricate the graded source HIGFET devices we will resort to selective area epitaxy which is a field currently under intense investigation. The graded source FET and the infra-red detector closely resemble the FET structures that are already proven and used in optoelectronic integrated circuits (OEICs) and microwave integrated circuits. Using interface engineering strategies, the frequency and small signal response of these devices can be increased. One such technique that uses a thin epitaxial GaP layer is proposed along with the device structrues. These devices can be used for smart pixel imaging applications.
Heterojunction FET structures are known in the art as illustrated in, for example, U.S. Pat. Nos. 4,558,337, Saunier et al, Dec. 10, 1985, 4,600,932, Norris, Jul. 15, 1986 and 4,866,490, Itoh, Sep. 12, 1989.
The '337 patent teaches group III-V compound high electron mobility FETs. In FIG. 1 of the patent, the structure illustrated includes two heterojunctions; one inverted (between layers 17 and 19) and one normal (between layers 19 and 21). The inventive structure of FIG. 2 includes two normal heterojunctions.
In the '932 patent, an enhanced mobility buried channel transistor structure is described. Referring to FIG. 1, the layer 11 is a semi-insulating GaAs layer. On top of the layer 11 is an undoped layer 12 and on top of the layer 12 is a doped layer 13. As seen in FIG. 2B, the doping of layer 13 is tapered. An undoped layer 14 covers layer 13. This removes the 2DEG layer from the top surface of the structure to minimize long range coulomb interaction with ionized impurities and interface scattering.
A MESFET structure is taught in the '490 patent. As seen in FIG. 4, the inventive structure includes a GaAs semi-insulating layer 1, a high purity AlAs layer 42 and a high purity Al.sub.x Ga.sub.l-x As layer 49. The electrode affinity of the layer 49 is graded, as shown in FIG. 5, such that, at the junction of layers 42 and 49, x=1, and at the top of layer 49, x=0.